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MITSUBISHI ICs (TV)
M64898GP
PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC DESCRIPTION
The M64898GP is a semiconductor integrated circuit consisting of PLL frequency synthesizer for TV/VCR /PC. It contains the prescaler with operating up to1.3GHz,4 band drivers and DC-DC converter for Tuning voltage.
PRESCALER INPUT GND SUPPLY VOLTAGE 1 SUPPLY VOLTAGE 2 BAND SWITCHING OUTPUTS fin GND VCC1 VCC2 BS4 BS3 BS2 1 2 3 4 5 6 7 8 9 10 20 Xin 19 ENA 18 DATA 17 CLK CRYSTAL OSCILLATOR ENABLE INPUT DATA INPUT CLOCK INPUT
PIN CONFIGURATION (TOP VIEW)
FEATURES
M64898GP
* * * * * * * * *
Built-in DC-DC converter for Tuning voltage 4 integrated PNP band drivers (Io=30mA, Vsat=0.2V typ@VCC1 to 10V ) Built-in prescaler with input amplifier (max=1.3GHz) PLL lock/unlock status display out put (Built-in pull up resistor) X'tal 4MHz is used to realize 3 type of tuning steps (Divider ratio 1/512, 1/640, 1/1024) Software compatible with M64892/M64893 Automatick switching of tuning step according to the number of data bits (62.5kHz at 18bits , 32.25kHz at 19bits) Built-in Power on reset system Small Package(SSOP)
16 LD/ftest LD/ftest OUTPUT 15 CONT fREF SWITCHING FILTER INPUT 14 Vin 13 Vtu 12 11 +B SWE TUNING OUTPUT SUPPLY VOLTAGE SWITCHING OUTPUT
BS1 DC-DCSUPPLY VDC VOLTAGE PEACK CURRENT lpk DETECT
Outline 20P2E-A
RECOMMENDED OPERATING CONDITION APPLICATION
PC, TV, VCR tuners Supply voltage range..............................................V CC1=4.5 to 5.5V VCC2=VCC1 to 10V Rated supply voltage...........................................................V CC1=5V VCC2=VCC1
BLOCK DIAGRAM
VCC1 3 CNT 15 VDC 9 SQ Xin 20 OSC f REF DIVIDER SELECTER DIV. R 11 SWE LATCH fin 1 AMP 1/8 LATCH 15 2 lpk 10
+
PHASE DETECTOR CHARGE PUMP CP LOCK DETECTOR 5 TEST LATCH 14 Vin Vreg 12 +B 15bit PROGRAMMABLE DIVIDER 13 Vtu OS
1/32,1/33
CLK 17 18/19-bit SHIFT REGISTER CONTROL
DATA 18
ENA 19 4 BAIS / BAND SWITCH DRIVER Power On Reset 4 VCC2 5 BS4 6 BS3 7 BS2 8 BS1 2 GND 16 LD/ftest
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MITSUBISHI ICs (TV)
M64898GP
PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC DESCRIPTION OF PIN
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 Symbol f in GND VCC1 VCC2 BS4 BS3 BS2 BS1 VDC Ipk SWE +B Vtu DC-DC power supply voltage Peack current detect Switching output Power supply voltage Tuning output Band switching outputs GND
Power supply voltage 1 Power supply voltage 2
Pin name Prescaler input Input for the VCO frequency. Ground to 0V.
Function
Power supply voltage terminal. 5.0V0.5V Power supply for band switching, Vcc1 to 10V PNP open collector method is used. When the band switching data is "H", the output is ON. When it is "L", the output is OFF. DC-DC power supply voltage terminal. 5.0V 0.5V When potential difference with VDC terminal becomes more than 0.33V by current limiting detector of DC-DC converter, the listing rises with off. DC-DC converter oscillator output. Power supply voltage for turning voltage. This supplies the tuning voltage. This is the output terminal for the LPF input and charge pump output. When the phase of the programmable divider output (f 1/N) is ahead compared to the reference
14
Vin
Filter input
(Charge pump output)
frequency (fREF), the "source" current state becomes active. If it is behind, the "sink" current becomes active. If the phases are the same, the high impedance state becomes active. Lock detector output. When loop of phase locked loop locked it, it rises with "H" level in "L" level or unlock. In control byte data input, the programmabule freq. divider output and reference freq. output is selected by the test mode. Set up reference frequency divider ratio. In "L" level, set it up in 1/640(19Bit) in setting "opening" in 1/1024(19Bit) or 1/512 (18Bit). Data is read into the shift register when the clock signal falls. Input for band SW and programmable freq. divider set up. This is normally at a "L". When this is at "H", data and clock signals are received. Data is read into the latch when the enable signal after the 18th signal of the clock signal falls or when the 19th pulse of the clock signal falls. 4.0MHz crystal oscillator is connected.
15
LD/ftest
Lock detect /Test port
16 17 18 19
CONT CLOCK DATA ENABLE
fREF Switchi Clock input Data input Enable input This is connected to the crystal oscillator.
20
X in
ABSOLUTE MAXIMUM RATINGS (Ta=-20C to +75C, unless otherwise noted)
Symbol VCC1 VCC2 VI VO VBSOFF IBSON tBSON Pd Topr Tstg Parameter Supply voltage 1 Supply voltage 2 Input voltage Output voltage Voltage applied when the band output is OFF Band output current ON the time when the band output is ON Power dissipation Operating temperature Storage temperature per 1 band output circuit 40mA per 1 band output circuit 3circuits are pn at same time, Ta=75C Conditions Pin3 Pin4 Not to exceed Vcc1 fREF output Ratings 6.0 10.8 6.0 6.0 10.8 40.0 10 255 -20 to +75 -40 to +125 Unit V V V V V mA sec mW C C
2
MITSUBISHI ICs (TV)
M64898GP
PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC RECOMMENDED OPERATING CONDITIONS (Ta=-20C to +75C, unless otherwise noted)
Symbol VCC1 VCC2 fopr1 fopr2 IBDL Parameter Supply voltage 1 Supply voltage 2 Operating frequency (1) Operating frequency (2) Band output current 5 to 8 Conditions Pin3 Pin4 Crystal oscillation circuit Normally 1 circuit is on. 2 circuits on at the same time is max. It is prohibited to have 3 or more circuits turned on at the same time. Ratings 4.5 to 5.5 VCC1 to 10.0 4.0 80 to 1300 0 to 30 Unit V V V MHz mA
ELECTRICAL CHARACTERISTICS (Ta=-20C to +75C, unless otherwise noted, Vcc1=5.0V, Vcc2=9.0V)
Symbol VIH VIL1 VIL2 IIH IIL1 IIL2 IIL3 VOH VOL VBS Iolk1 VtoH VtoL Icpo IcpLK ICC1 ICC2A ICC2B Parameter "H" input voltage "L" input voltage "L" input voltage "H" input current "L" input current "L" input current "L" input current "H" output voltage "L" output voltage Output voltage Leak current Output voltage "H" Output voltage "L" "H" output current Test pin 17 to 19 15 17 to 19 17 to 19 15 17, 19 18 16 16 5 to 8 5 to 8 13 13 14 14 3 4 4 4 9 12 11 10 Test conditions Min. 3.0 - - - - - - 5.0 - 11.6 - 30.5 - - - - - - - - 28 - - Limits Typ. Max. VCC1+0.3 - - 0.4 - 1.5 - 10 -50 -80 -6 -10 -18 -30 - - 0.3 0.5 11.8 - - 0.2 270 - 20 - 4.0 34.0 1.3 31 571 330 -10 - 0.4 370 50 30 0.3 6.0 36.0 3.0 35 - - Unit V V V A A A A V V V A V V A nA mA mA mA mA mA V kHz mV
Input terminals
Lock output Band SW Tuning output Charge pump
VCC1=5.5V, Vi=4.0V VCC1=5.5V, Vi=0V VCC1=5.5V, Vi=0.5V VCC1=5.5V, Vi=0.5V VCC1=5.5V VCC1=5.5V VCC2=9V, Io=-30mA VCC2=9V, Band SW is OFF Vo=0V +B=31V +B=31V VCC1=5.0V, Vo=2.5V VCC1=5.0V, Vo=2.5V VCC1=5.5V VCC2=9V VCC2=9V VCC2=9V, Io=-30mA VCC1=5.5V VCC1=5.5V VCC1=5.5V VCC1=5.5V
Leak current Supply current 1 Supply current 2 4 circuits OFF 1 circuits ON, Output open Output current 30mA
ICC2C DC-DC Converter ICCdc Supply current (action) Vdo fOSC Vipk
Output voltage OSC frequency Current limit detect voltage
The typical values are at VCC1=5.0V, VCC2=9.0V, Ta=+25C.
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MITSUBISHI ICs (TV)
M64898GP
PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC SWITCHING CHARACTERISTICS (Ta=-20C to +75C, unless otherwise noted, Vcc1=5.0V, Vcc2=9.0V)
Symbol fopr Parameter Prescaler operating frequency Test pin 1 Test conditions VCC1=4.5 to 5.5V Vin=Vinmin to Vinmax 80 to 100MHz VCC1=4.5 100 to 950MHz to 5.5V 950 to 1300MHz Min. 80 -24 -27 -15 1 2 1 3 3 1 - - 5 5 Limits Typ. - - - - - - - - - - - - - - - - - - - - 1 1 - - Max. 1300 4 4 4 Unit MHz
Vin tPWC tSU (D) tH (D) tSU (E) tH (E) tINT tr tf tBT tBCL
Operating input voltage Clock pulse width Data setup time Data hold time Enable setup time Enable hold time Enable data interval time Rise time Fall time Next enable prohibit time Next clock prohibit time
1 17 18 18 18 18 19, 18
dBm s s s s s s s s s s
VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V 17, 18, 19 VCC1=4.5 to 5.5V 17, 18, 19 VCC1=4.5 to 5.5V 19 VCC1=4.5 to 5.5V 17, 19 VCC1=4.5 to 5.5V
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MITSUBISHI ICs (TV)
M64898GP
PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC METHOD OF SETTING DATA
The programmable divider ratio uses 15bits. Setting up the band switching output uses 4bits. The test mode data uses 8bits. The total bits used is 27bits. Data is read in when the enable signal is "H" and the clock signal falls. The band switching data is read in at the 4th pulse of the clock signal. The programmable counter data is read into the latch by the fall of the enable signal after the 18th pulse of the clock signal or the fall of the 19th pulse of the clock signal. When the enable signal goes to "L" before the 18th pulse of the enable signal, only the band SW data is updated and other data is ignored. Automatic judgment facility comes being it, and, as for Shift resister, CONT terminal rises by 18/19 bits at the time of "L". At the time of data of 18 bits, M9 bit of Programable divider is done reset of, and it is established in reference frequency divider ratio 1/512. At the time of 19 bits,reference frequency divider ratio is established in 1/1024. When reference frequency divider ratio was established in 1/640 by 19 bits at the time of "opening" CONT terminal, and it became "L" before 19 pulse enable signal, only band SW data are renewed, and other data are ignored.
(1) Transfer of the 18th bit data (CONT terminal is "L" ) Data is latched by the fall of the enable signal after the 18th clock signal. At this time, the divider of the 1/512 of the reference frequency is used.
ENA BS4 DATA BS3 BS2 BS1 28 M8 27 M7 26 M6 25 M5 24 M4 23 M3 22 M2 21 M1 20 M0 24 S4 23 S3 22 S2 21 S1 20 S0
CLK BAND SW DATA M COUNTER DIVIDER RATIO SETTING READ INTO LATCH S COUNTER DIVIDER RATIO SETTING READ INTO LATCH
(2) Transfer of the 19th bit data (CONT terminal is "L" or "open") The data is latched at the 19th pulse of the clock signal. Reference frequency divider ratio is established in 1/1024 in case of "L" CONT terminal at this time. Reference frequency divider ratio is established in 1/640 in case of "opening" CONT terminal. Invalid the clock signal after 19th pulse. Notice) When CONT terminal is "L", to change reference frequency, set up as ENA in "L" after 19th pulse of clock signal by all means.
ENA BS4 DATA BS3 BS2 BS1 29 M9 28 M8 27 M7 26 M6 25 M5 24 M4 23 M3 22 M2 21 M1 20 M0 24 S4 23 S3 22 S2 21 S1 20 S0
CLK BAND SW DATA M COUNTER DIVIDER RATIO SETTING READ INTO LATCH S COUNTER DIVIDER RATIO SETTING READ INTO LATCH
5
MITSUBISHI ICs (TV)
M64898GP
PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC HOW TO SET THE DIVIDING RATIO OF THE PROGRAMMABLE DIVIDER
(1) Transfer of the 18th bit data (CONT terminal is "L" ) Total divider N is given by the following formulas in addition to the prescaler used in the previous stage. N=8 * (32M+S) M : 9 bit main counter divider S : 5 bit swallow counter divider The M and S counters are binary the possible ranges of divider are as follows. 32M511 0S31 Therefore, the range of divider N is 8,192 to 131,064. The tuning frequency fVCO is given in the following equations. fVCO=fREFxN =7.8125x8x(32M+S) =62.5x(32M+S) [kHz] Therefore, the tuning frequency range is 64MHz to 1023.9375MHz. (2) Transfer of the 19th bit data (CONT terminal is "L" ) Total divider N is given by the following formulas in addition to the prescaler used in the previous stage. N=8 * (32M+S) M : 10 bit main counter divider S : 5 bit swallow counter divider The M and S counters are binary the possible ranges of divider are as follows. 32M1023 0S31 as follows. 32M1023 0S31 Therefore, the range of divider N is 8,192 to 262,136. The tuning frequency fVCO is given in the following equations. fVCO=fREFxN =6.25x8x(32M+S) =50.0x(32M+S) [kHz] But, the tuning frequency range is 51.2MHz to 1300MHz from the maxmum prescaler operating frequency. (3) Transfer of the 19th bit data (CONT terminal is "open") Total divider N is given by the following formulas in addition to the prescaler used in the previous stage. N=8 * (32M+S) M : 10 bit main counter divider S : 5 bit swallow counter divider The M and S counters are binary the possible ranges of divider are MHz. Therefore, the range of divider N is 8,192 to 262,136. The tuning frequency fVCO is given in the following equations. fVCO=fREFxN =3.90625x8x(32M+S) =31.25x(32M+S) [kHz] Therefore, the tuning frequency range is 32MHz to 1023.96875
TEST MODE DATA SET UP METHOD
The data for the test mode uses 20 to 27bits. Data is latched when the 27th clock signal falls. (1) When transferring 3-wire 27 bit data
ENA 1 CLK BAND SW DATA M COUNTER DIVIDER RATIO SETTING S COUNTER DIVIDER RATIO SETTING X X T2 T1 T0 RSa RSb 0S TEST DATA SETTING READ INTO LATCH 19 20 27
(2) Test Mode Bit Set Up X RSa, Rsa OS :Random, 0 or 1.normal "0" :Set the frequency divider of the reference frequency :Set up the tuning amplifier T0, T1,&T2 :Set up test modes
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MITSUBISHI ICs (TV)
M64898GP
PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC
Setting up for the test mode T2 0 0 1 1 1 1 T1 0 1 1 1 0 0 T0 X X 0 1 0 1 Charge pump
Normal operation
Set up the tuning amplifier 12 pin output LD LD LD LD fREF f1/N Mode
Normal operation
High impedance Sink Source High impedance High impedance
Test mode Test mode Test mode Test mode Test mode
OS 0 1
Tuning voltage output ON OFF
Mode Normal Test
Power on reset operation (Initial state the power is turned ON)
BS4 to BS1 Charge pump : OFF : High impedance : OFF : 270A : 1/1024 :H
Set up for the reference Frequency divider ratio RSa 1 0 X RSb 1 1 0 Divider ratio 1/512 1/1024 1/640
Tuning amplifier Charge pump current Frequency divider ratio Lock detect
Charge pump current is replaced by 70A when locks it by automatic change facility.
TIMING DIAGRAM
tr tf VIH 10% tINT tINT tBT VIH 90% 10% VIL tr 90% 10% VIL tPWC tSU(D) tSU(E) tH(D) tr tf tH(E) tBCL tf VIH
ENABLE
90% 1.5V 10%
90%
VIL
90% DATA 1.5V 10%
90% 1.5V CLOCK 10%
CRYSTAL OSCILLATOR CONNECTION DIAGRAM
16
Crystal oscillator characteristics Actual resistance : less then 300 Load capacitance : 20pF 18pF
4MHz
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MITSUBISHI ICs (TV)
M64898GP
PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC APPLICATION EXAMPLE
BUILT-IN PLL TUNER IF AGC
IF
AGC
VHF 4-BAND TUNER UHF
AFT
Note) Filter constant is for reference. Add a capacitor to stabilize the filter circuit.
+B
BS4
BS3
BS2
BS1
LO
VT
VCC1 to 9V 1000pF 680pF
0.01F 56k 100pF 56k 0.1F
33H 0.1F 43
22k 13 9
68H 10 11
M64898GP
4
5
6
7
8
1
14
AMP BIAS CIRCUIT Q S BAND DRIVER 4 1/32 1/33 1/8 CHARGE PUMP +PHASE DETECTOR Vreg SELECTER 12 9/10 18/19 bit SHIFT RESISTER DATA LATCH LOCK DETECTOR OSC DIVIDER 2 1.5F R
3 +5V MAIN COUNTER
POWER ON RESET
SWALLOW COUNTER
5
VCC1=5V
15 18pF 20 4MHz
1000pF
19
17
18
15
DATA MCU
CLK
ENA
LD/ftest
Units Resistance : Capacitance : F
8

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